Case study
The Compute Register
Thirteen AI accelerators seen two ways: what each can run, and what it means to depend on it. Memory and model fit for CTOs; makers, factories, software lock-in, and availability for boards. A sample from our compute analysis, which is shared in full with clients during consulting.
Memory and bandwidth per chip
Memory decides how large a model fits on one chip; bandwidth decides how fast it answers. Hatched bars are chips announced or ramping but not yet broadly available. Select a name to open its card.
Chips
Each card pairs the engineering facts with the questions a buyer has to answer: who makes it, where it is fabricated, how you can get it, and how hard it would be to leave.
Will it fit?
Pick an open-weight model from the Model Register and a workload. The table shows how many of each chip you would need to hold the model and its working memory. The highlighted rows need the fewest chips.
Where the dependence sits
Choosing a chip is also choosing a supply chain and a software ecosystem. These are the concentrations behind the thirteen chips in this sample.
Rent, API, or buy?
Most organizations should not start by buying hardware. These rules of thumb follow the same logic as the Matrix: match the commitment to the evidence.
Start with an API
While you are still proving the use case, pay per token through a hosted model. No hardware, no idle cost. Use sample or non-sensitive data, because it leaves your premises.
Rent when data or volume demands it
Rent GPUs when data must stay in your country, or when steady volume makes per-token pricing more expensive than a rented server. Start with one role, not the whole stack.
Buy only for steady, long-lived load
Buying makes sense when usage is predictable for years and you can keep the chips busy. Chip generations now arrive yearly, so idle hardware loses value fast.
Keep an exit
Prefer chips and clouds you could leave. Cloud-only accelerators can be cheaper, but they tie your models, tools, and staff skills to one provider.
Method and sources
Specifications
Memory and bandwidth per chip as published by each maker or reported from launch events, checked in November 2026. Figures for chips not yet broadly available can still change; NVIDIA and AMD have both revised HBM4 bandwidth figures this year.
Model fit
Weights take total parameters times bytes per parameter; the working memory (KV cache) takes the model’s cache per token times context times concurrent requests, from the Model Register. We assume 90% of each chip’s memory is usable. Activations and framework overhead add more.
Dependence
Maker, fabrication, memory supply, software ecosystem, and how the chip can be obtained. Lock-in reflects how hard it is to move models and tooling elsewhere, not the quality of the chip.
A sample of thirteen accelerators from our compute analysis, published as a case study. The full analysis is shared with clients during consulting engagements. Not a recommendation to buy or rent any product; export-control and licensing questions need legal advice.
Planning where your models will run?
We size the hardware, compare renting, APIs, and buying, and map the dependence behind each option, under a mutual non-disclosure agreement.